Real time traffic simulator for self-adaptive navigation system validation

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Pegasus: Performance Engineering for Software Applications Targeting HPC Systems

Developing and optimizing software applications for high performance and energy efficiency is a very challenging task, even when considering a single target machine. For instance, optimizing for multicore-based computing systems requires in-depth knowledge about programming languages, application programming interfaces, compilers, performance tuning tools, and computer architecture and organization. Many of the tasks of performance engineering methodologies require manual efforts and the use of different tools not always part of an integrated toolchain. This paper presents Pegasus, a performance engineering approach supported by a framework that consists of a source-to-source compiler, controlled and guided by strategies programmed in a Domain-Specific Language, and an autotuner. Pegasus is a holistic and versatile approach spanning various decision layers composing the software stack, and exploiting the system capabilities and workloads effectively through the use of runtime autotuning. The Pegasus approach helps developers by automating tasks regarding the efficient implementation of software applications in multicore computing systems. These tasks focus on application analysis, profiling, code transformations, and the integration of runtime autotuning. Pegasus allows developers to program their strategies or to automatically apply existing strategies to software applications in order to ensure the compliance of non-functional requirements, such as performance and energy efficiency. We show how to apply Pegasus and demonstrate its applicability and effectiveness in a complex case study, which includes tasks from a smart navigation system

A 10 Mbit/s Upstream Cable Modem with Automatic EqualizationPatrick Schaumont Radim Cmar Serge Vernalde Marc Engels

A fully digital QAM16 burst receiver ASIC is presented. The BO4 receiver demodulates at 10 Mbit/s and uses an advanced signal processing architecture that performs perburst automatic equalization. It is a critical building block in a broadband access system for HFC networks. The chip was designed using a C++ based flow and is implemented as a 80 Kgate 0.7u CMOS standard cell design. 1 Introduction The widespread use of Internet is opening a pathway to emerging multimedia consumer networks and applications. These require a broadband data communications link to be established in the access network that connects the consumer to a core service network. The hybrid fiber-coax (HFC) access network that is currently in use for cable TV, is considered as an attractive candidate [4]. We have developed a chip that is embedded in an HFC head-end and that demodulates data transmitted from the consumer set-top. This chip is a fully digital burst receiver, characterized as shown in table 1. The chip..

Hardware reuse at the behavioral level

Standard interfaces for hardware reuse are currently de ned at the structural level. In contrast to this, our contribution de nes the reuse interface at the behavioral registertransfer (RT) level. This promotes direct reuse of functionality and avoids the integration problems of structural reuse. We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

DSL and Autotuning Tools for Code Optimisation on HPC Inspired by Navigation Use Case

When targeting high performance computing (HPC) platforms, improving the performance and scalability of code is often a tedious and time consuming task. The code has to be executed and even compiled many times under different conditions in order to observe its behaviour on the target hardware. These experiments are performed with the goal of estimating an optimal set of the run-time environment parameters to achieve optimal performance and energy efficiency. This optimization task is best performed automatically, but due to the heterogeneous nature of the source codes and the HPC platform, fully automation is often hard to implement. The domain specific language (DSL) and toolflow approach proposed in the ANTAREX project ( www.antarex-project.eu ) can provide the mechanisms needed for addressing properly the problems previously described. The DSL being developed is based on the LARA DSL [1] and allows to specify strategies for code instrumentation and code transformations, including the required code adaptation for dynamic autotuning [2]. By using instrumentation strategies, the measurements can be integrated seamlessly into the development process, e.g., as a standalone stage in the continuous integration process. The ANTAREX project plans to demonstrate the usage of the LARA DSL and the autotuning approach on two use cases in cooperation with commercial partners, HPC Accelerated Drug Discovery System (Dompe), and the Self-adaptive Navigation System (Sygic). The poster is focused on the presentation of the DSL and autotuning tools for the self-adaptive navigation system use case, which basic idea is to combine server-side and client-side data knowledge and their routing capabilities to provide the most efficient navigation system in the context of smart cities. In such a use case, we assume a significantly large portion of drivers participating in the system. The efficiency is essential given that the routing system needs to serve many requests requiring potentially huge computation power. Then still, even without limits to be reached, it is desirable to optimize the execution of such a system with respect to the energy efficiency. The probabilistic Time-Dependent Travel Time Computation algorithm [3] has been selected for the demonstration of DSL and autotuning tools usage in the Self-adaptive Navigation System. The input for the algorithm is a departure time and a selected route composed as a line of road segments. A Monte Carlo simulation (MCS) is used for the computation of the probability distribution of travel time for the selected route. The simulation randomly selects probabilistic speed profiles on road segments and computes travel time at the end of the route. Many MCS iterations are needed to obtain enough travel times for the construction of the probability distribution of travel time. The number of simulation iterations greatly affects the precision of the result

Pegasus: performance engineering for software applications targeting HPC systems

Developing and optimizing software applications for high performance and energy efficiency is a very challenging task, even when considering a single target machine. For instance, optimizing for multicore-based computing systems requires in-depth knowledge about programming languages, application programming interfaces (APIs), compilers, performance tuning tools, and computer architecture and organization. Many of the tasks of performance engineering methodologies require manual efforts and the use of different tools not always part of an integrated toolchain. This paper presents Pegasus, a performance engineering approach supported by a framework that consists of a source-to-source compiler, controlled and guided by strategies programmed in a Domain-Specific Language, and an autotuner. Pegasus is a holistic and versatile approach spanning various decision layers composing the software stack, and exploiting the system capabilities and workloads effectively through the use of runtime autotuning. The Pegasus approach helps developers by automating tasks regarding the efficient implementation of software applications in multicore computing systems. These tasks focus on application analysis, profiling, code transformations, and the integration of runtime autotuning. Pegasus allows developers to program their strategies or to automatically apply existing strategies to software applications in order to ensure the compliance of non-functional requirements, such as performance and energy efficiency. We show how to apply Pegasus and demonstrate its applicability and effectiveness in a complex case study, which includes tasks from a smart navigation system.Web of Science48375473

ANTAREX - AutoTuning and adaptivity approach for energy efficient eXascale HPC systems

The main goal of the ANTAREX project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach

The main goal of the ANTAREX1project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management